1. Field of the Invention
The present invention relates to a memory cell sense amplifier.
2. Description of the Related Art
The present invention more particularly relates to a sense amplifier comprising a read node directly or indirectly linked to a memory cell, an active stage connected to the read node and comprising means for supplying a read current to the read node, and a data output linked to the output of a comparator which compares to a reference voltage the voltage present on a node of the active stage, this voltage being representative of the state of conductivity of the memory cell.
The present invention particularly, but not exclusively applies to non-volatile memories, like EEPROM and FLASH EEPROM memories, and more particularly to PCM memories (phase change memory). In these memories, each memory cell can take two distinct states, i.e., an erased state and a programmed state. In phase change memories, each memory cell comprises an alloy able for example to take a crystalline state and an amorphous state, passing from one to the other being made by cycles for heating/cooling the alloy, in particular according to the duration of the cycle for cooling or heating.
Classically, a sense amplifier is used to detect the programmed or erased state of a memory cell of a non-volatile memory, by comparing the value of a current flowing through the memory cell to a reference current. The fact that the memory cell is programmed or erased is rendered indeed by a determined state of conductivity of the memory cell, and corresponds by convention to a determined value of the datum stored by the memory cell, for example 1 for the programmed state and 0 for the erased state.
FIG. 1 schematically shows a standard architecture of a sense amplifier SA1 of a non-volatile memory. On this figure and in the description of the present invention, the transistors of the PMOS type are indicated by references beginning with “TP” and the NMOS transistors are indicated by references beginning with “TN”. The sense amplifier SA1 comprises a control stage CST1, a read stage RST1 comprising a read node Sin, and an output stage OST comprising a data output Sout, these stages being electrically powered by a voltage Vcc.
The control stage CST1 comprises transistors TP1 and TP2 mounted in series with parallel-connected transistors TN2 and TN1. The transistor TP1 receives on its source terminal the voltage Vcc, and on its gate terminal a reference voltage Vrefp. The drain terminal of the transistor TP1 is connected to the source terminal of the transistor TP2. A control signal EN1 is applied to the control gate of the transistors TP2 and TN2. The drain terminal of the transistor TP2 is connected to the drain terminals of the transistors TN1 and TN2 which source terminals are put to the ground. The gate terminal of the transistor TN1 is connected to the read node Sin.
The read stage RST1 comprises two transistors TP3 and TN3 mounted in series. The transistor TP3 receives the voltage Vcc on its source terminal and the voltage Vrefp on its gate terminal. The drain terminal of the transistor TP3 and the drain terminal of the transistor TN3 are connected to a node N1 which is connected to the input of the output stage OST.
The source terminal of the transistor TN3 is connected to the read node Sin, on which a voltage Vs called “read voltage” appears. The gate terminal of the transistor TN3 is connected to a node CH which receives a voltage V(CH) taken from the drain terminal of the transistor TP2 of the control stage CST1. The read stage further comprises a precharge transistor TN4 mounted in parallel with the transistor TP3 and which drain terminal receives the voltage Vcc. The gate and the source terminals of the transistor TN4 are respectively connected to the data output Sout of the sense amplifier SA1, and to the node N1.
The output stage OST comprises a comparator CP comprising a positive output receiving the voltage Vrefp and a negative input receiving a voltage V(N1) present on the node N1. The output of the comparator which forms the data output Sout of the sense amplifier, is in addition connected to the gate terminal of the transistor TN4.
On FIG. 1, the read node Sin is linked to a non-volatile memory cell MC(i,j,k) of a memory array MA (only one memory cell is shown for the sake of simplicity), for example by means of a word column k selection transistor TS(k) and of a bit line BL(j,k). The transistors TS(k) are driven by a column selection signal SEL(k) from a column decoder (not shown). As an example application, the memory cell belongs to an EEPROM memory, and thus comprises a floating gate transistor which source terminal is linked to the ground and which gate terminal receives a read voltage Vr during a read phase. The threshold voltage of the floating gate transistor depends on its programmed or erased state and the read voltage Vr is chosen between the threshold voltage at the programmed state and the threshold voltage at the erased state. Thus, when the read voltage Vr is applied, the floating gate transistor is highly conducting if it is in the programmed state (low threshold voltage), or conversely little conducting, or even blocked if it is in the erased state (high threshold voltage).
The sense amplifier is inactive when the signal EN1 is 1 (=Vcc) and the voltage Vrefp is equal to Vcc. The transistor TN2 is then conducting. The transistor TP2 is blocked, and the drain terminal of the transistor TN1 is linked to the ground. Therefore, there is no current flowing through the control stage CST1. The transistors TP1 and TP3 are blocked and there is no current flowing through the read stage RST1.
The reading of a memory cell MC(i,j,k) is preceded by a phase of address decoding, performed by the column decoder, making it possible to link the bit line BL(j,k) of the memory cell to the read node Sin of the sense amplifier.
The reading of the memory cell comprises a phase of precharging the bit line BL(j,k), and a phase of reading the datum memorized in the memory cell. The read voltage Vr is applied from the precharge phase to the gate terminal of the floating gate transistor of the memory cell to be read. The sense amplifier SA1 is first activated by bringing the voltage Vrefp to the value Vcc−Vtp, where Vtp is the threshold voltage of the PMOS transistors. The transistors TP1 and TP3 then operate as current generators and respectively supply currents Ib and Ir in their respective stages.
The precharge phase is started by setting the signal EN1 to 0. The transistor TN2 blocks and the transistor TP2 becomes conducting. The voltage V(CH) on the node CH which is applied to the gate terminal of the transistor TN3 increases and the latter becomes conducting. The transistors TP3 and TN4 are also conducting (the voltage V(Sout) at the data output Sout is at the high level), and a precharge current is supplied to the read node Sin. The transistor TN4 is used to accelerate the precharge phase and consequently, to diminish the global read time, by supplying a current Ifb which adds to the current Ir supplied by the transistor TP3. The precharge current, equal to Ir+Ifb, is used to charge stray capacitances located in the bit line BL(j,k) and to rapidly bring the read voltage Vs to a determined value which is substantially equal to the threshold voltage Vtn of the NMOS transistors. In addition, the limitation of the voltage Vs, performed by the transistor TN3 allows the floating gate transistor of the memory cell to be protected against a phenomenon called “drain stress”, which is rendered by an involuntary injection of charges into the floating gate causing a parasitic programming of the memory cell.
When the determined value of the read voltage Vs is reached, the transistor TN1 becomes conducting. The voltage V(CH) on the node CH decreases and stabilizes at a value such that, on the one hand, the currents in the transistors TP1 and TN1 are identical, and on the other hand, the current supplied by the transistor TN3 to the read node corresponds to the current Ic imposed by the memory cell currently being read.
At the end of the precharge phase, the voltage V(N1) on the node N1 is near the voltage Vrefp. There are two possible situations: either the memory cell is programmed and a 1 must be read by the sense amplifier, or the memory cell is erased and 0 must be read. If a 1 must be read, the cell current Ic is superior to the reference current Ir. The voltage V(N1) on the node N1 remains slightly inferior to the voltage Vrefp. The signal supplied by the comparator CP on the data output Sout of the sense amplifier remains at a level of voltage high enough to maintain the transistor TN4 in the conducting state. The transistor TN4 then supplies a current equal to the difference Ic−Ir between the current Ic imposed by the memory cell and the reference current Ir supplied by the transistor TP3.
If a 0 must be read, the current Ic in the memory cell to be read is lower than the reference current Ir. In that case, the voltage V(N1) on the node N1 increases to a level higher than the voltage Vrefp. The signal on the data output Sout then goes to the low state.
It turns out that this type of detection circuit has a limitation due to the fact that the voltage Vs on the read node Sin, which corresponds to the voltage of the bit line BL(j,k), must be forced to a value slightly superior to the threshold voltage Vtn (typically ranging from 0.8 V to 1 V), because of a slight over-voltage required by the transistor TN1 to supply the current Ib. However, in certain applications, the bit line must be biased to a level lower than this threshold voltage to reduce the constraints caused by the current Ic flowing through the memory cell, which could damage data integrity.
In particular, in PCM memories, the current Ic flowing through a memory cell during a read phase should be limited so as to reduce the heating of the memory cell, and thus avoid undesirable thermal effects that may particularly cause the recrystallization of the phase change material from its amorphous state, and thus a corruption of memorized data.
To reduce the read voltage Vs applied to the read node, the threshold voltage Vtn may be reduced. However, this voltage constitutes a technological parameter of the NMOS transistors of the sense amplifier. In fact, this parameter is linked to the manufacturing technique used to make the amplifier, and is substantially invariant for a given manufacturing technique.